Modeling Engineer
Neurophos
Other Engineering
San Francisco, CA, USA
Posted on Jan 25, 2026
About Neurophos
We are developing an ultra-high-performance, energy-efficient photonic AI inference system. We’re transforming AI computation with the first-ever metamaterial-based optical processing unit (OPU).
As AI adoption accelerates, data centers face significant power and scalability challenges. Traditional solutions are struggling to keep up, leading to rapidly rising energy consumption and costs. We’re solving both problems with an OPU that integrates over one million micron-scale optical processing components on a single chip. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving large-scale AI inference performance.
We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. We have also been recognised on the EE Times Silicon 100 list for several consecutive years.
Join us and shape the future of optical computing!
Location: San Francisco Bay Area or Austin, TX. Full-time onsite position.
Position Overview
We are seeking hardware modeling engineers to develop functional and performance models of our next-generation optical computing platform. You will work alongside experienced modeling engineers to implement models of novel compute blocks including optical GEMM engines, SRAM vector processors, and dataflow architectures. This role is ideal for new graduates with strong academic backgrounds or engineers with 3+ years of experience looking to transition into hardware modeling for cutting-edge AI accelerators.
Key Responsibilities
We are developing an ultra-high-performance, energy-efficient photonic AI inference system. We’re transforming AI computation with the first-ever metamaterial-based optical processing unit (OPU).
As AI adoption accelerates, data centers face significant power and scalability challenges. Traditional solutions are struggling to keep up, leading to rapidly rising energy consumption and costs. We’re solving both problems with an OPU that integrates over one million micron-scale optical processing components on a single chip. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving large-scale AI inference performance.
We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. We have also been recognised on the EE Times Silicon 100 list for several consecutive years.
Join us and shape the future of optical computing!
Location: San Francisco Bay Area or Austin, TX. Full-time onsite position.
Position Overview
We are seeking hardware modeling engineers to develop functional and performance models of our next-generation optical computing platform. You will work alongside experienced modeling engineers to implement models of novel compute blocks including optical GEMM engines, SRAM vector processors, and dataflow architectures. This role is ideal for new graduates with strong academic backgrounds or engineers with 3+ years of experience looking to transition into hardware modeling for cutting-edge AI accelerators.
Key Responsibilities
- Implement functional and performance models of hardware compute blocks
- Develop simulation components within the YinYang (libyy) event-driven framework
- Write clean, modular C++ code for hardware simulation
- Integrate models with RTL simulation and validation infrastructure
- Build test cases and validate model correctness
- Contribute to trace generation and analysis infrastructure
- Collaborate with senior engineers on modeling methodology
- Debug and optimize simulation performance
- Document models and interfaces for team use
- BS in Electrical Engineering, Computer Engineering, or Computer Science (MS or PhD preferred)
- 3+ years of software development experience (exceptional new graduates with strong academic projects considered)
- Strong programming skills in C++ or C
- Understanding of computer architecture fundamentals (pipelines, memory hierarchy, basic processor concepts)
- Coursework or project experience in computer architecture, digital design, or hardware systems
- Ability to read and understand technical specifications
- Strong problem-solving and debugging skills
- Effective communication and teamwork abilities
- Python scripting experience
- Experience with hardware simulation, modeling, or verification
- Familiarity with SystemC, Verilator, or hardware description languages
- Background in software development for performance-critical applications
- Understanding of event-driven programming or simulation frameworks
- Exposure to computer architecture research or projects
- Knowledge of ML workloads and neural network operations
- Experience with Git, Linux development environments, and build systems
- Coursework in digital logic, computer organization, or VLSI design
- A pivotal role in an innovative startup redefining the future of AI hardware.
- A collaborative and intellectually stimulating work environment.
- Competitive compensation, including salary and equity options.
- Opportunities for career growth and future team leadership.
- Access to cutting-edge technology and state-of-the-art facilities.
- Opportunity to publish research and contribute to the field of efficient AI inference.
