Your space-enabled career begins here

Space-based technologies are the building blocks of these pillars of innovation:

Search for credible job opportunities with top entrepreneurial space companies.

Senior Technical Staff Engineer - Software (Design Infrastructure & Methodologies)



IT, Other Engineering, Design
San Jose, CA, USA
Posted on Thursday, June 6, 2024

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description:

Microchip Technology FPGA Business group is seeking a highly skilled and experienced System Architect to join our dynamic team. The successful candidate will be responsible for leading cross-functional teams to develop and maintain methodologies for development of future FPGAs and for leading automation of the integration of various high performance IPs, that meet market & customer requirements across a broad range of application spaces.

This position is in the Silicon Architecture team of Microchip’s FPGA Division. Microchip is a major supplier of low-power and highly-reliable field-programmable gate arrays (FPGAs). Our FPGAs are used in a wide variety of applications, including embedded vision; digital signal processing; machine learning; industrial and medical equipment; and satellites. Microchip is also a pioneer in embedding RISC-V processors in FPGAs.

The successful applicant will work as part a core team to develop future FPGA device products and will collaborate with other engineering disciplines to manage planning, coordination and orchestration of modeling, developing, verification, and integration of various necessary system components such as IO, hard IP blocks, hard & soft IP solutions, that interoperate with overall configuration and security features to deliver performant FPGA products.

Key Responsibilities:

  • Lead cross-functional teams to develop methodologies to improve quality and schedule of Microchip FPGA BU products
  • Lead cross-functional teams to establish methodologies to incorporate Single-Source-Of-Truth in product development to improve integration as well as cross-functional team communication, productivity and product quality
  • Work on ASIC & FPGA IP development, integration, and deployment for System Integration of ASIC IP
  • Understand customer use models and the role of IP in overall system architecture
  • Work cross-functionally with other architects, designers, and back-end implementation teams
  • Lead and manage other engineers in the team


  • 12.5+ years of industrial experience
  • Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, or a related field required; Master's degree or above is preferred.
  • Proven experience in ASIC & FPGA IP development, integration, and deployment, including all stages of development from Synthesis, constraint management, place & route, floorplanning, timing closure, CDC/RDC
  • Knowledge and experience with system-level performance modeling in TLM/SystemC/Other will be an advantage
  • Proven experience in HDL, Verilog, SystemVerilog
  • Experience in technical leadership and people management
  • Proven ability to work cross-functionally with other architects, designers, and back-end implementation teams
  • Knowledge and experience with Synopsys & Cadence ASIC flows
  • Scripting for EDA in Perl, Python, Make, Tcl

Travel Time:

0% - 25%

Physical Attributes:

Feeling, Hearing, Other, Seeing, Talking, Works Alone, Works Around Others

Physical Requirements:

80% Sitting, 10% Walking, 10% Standing, Usual Business Hours

Pay Range:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below:

Benefits of working at Microchip

The annual base salary range for this position, which could be performed in California, is $75,000 - $232,000.*

*Range is dependent on numerous factors including job location, skills and experience.

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.

For more information on applicable equal employment regulations, please refer to the EEO is the Law Poster and the EEO is the Law Poster Supplement. Please also refer to the Pay Transparency Policy Statement.