Your space-enabled career begins here

Efficient is seeking an experienced and technically strong Verification & Validation Manager to lead the end-to-end strategy and execution of verification and validation — including pre-silicon verification, emulation, and post-silicon validation and test. This leader will own the processes, infrastructure, teams, and outcomes that ensure our processors meet the highest standards of quality, performance, and reliability.

This individual will manage and scale a multidisciplinary V&V organization, work cross-functionally with architecture, digital design, software, and manufacturing teams, and interface closely with external verification and silicon validation vendors. As a technical leader, this person will shape company-wide methodologies that support aggressive product roadmaps and world-class silicon execution.

This is a rare opportunity to build and lead a full-stack V&V function at a fast-moving startup redefining energy-efficient compute.

Key Responsibilities

Leadership & Strategy

• Own the holistic verification and validation strategy — pre-silicon verification, emulation, and post-silicon validation.
• Define and implement scalable methodologies, processes, and infrastructure that ensure thorough coverage, high-quality implementation and predictable execution across multiple product generations.
• Build, manage, and mentor a growing team consisting of DV engineers, emulation engineers, silicon validation/test engineers (including senior-level reports), and compiler/program-driven verification engineers.
• Create organizational plans, establish goals and KPIs, drive performance management, and oversee hiring for new V&V roles.
• Provide regular status updates, risk assessments, and technical insights to senior leadership and stakeholders.

Pre-Silicon Verification & Digital Verification

• Oversee development of comprehensive SoC-level and subsystem-level verification plans, ensuring alignment with architectural and design requirements.
• Direct the creation, maintenance, and execution of SystemVerilog/UVM-based test benches, stimuli, agents, checkers, and coverage models.
• Set and drive the vericiation roadmap, milestone plans, and coverage closure strategies.
• Manage external verification service vendors; ensure deliverables, quality, and timelines are met.
• Lead debugging efforts for complex design and functional issues in collaboration with design, architecture, and software teams.

Emulation & Pre-Silicon Acceleration

• Define and lead the company’s emulation and FPGA-based prototyping strategy.
• Oversee emulation platform bring-up, test content migration, and performance/debug methodologies.
• Ensure emulation infrastructure supports both architecture validation and early software development.
• Partner with firmware/software teams to enable pre-silicon validation at scale.

Post-Silicon Validation & Test

• Oversee planning and execution of silicon bring-up, characterization, validation, test-flow development, and productization.
• Drive the creation of the New Product Introduction (NPI) plan for validation, test hardware/software, and manufacturing readiness.
• Manage relationships with external silicon validation and test vendors — establish scope, ensure performance, and maintain accountability.
• Direct post-silicon debug, including digital, analog, mixed-signal, and timing-related issues.
• Guide validation engineers in developing repeatable, robust silicon validation methodologies.
• Review and deliver detailed silicon reports, characterization results, and technical summaries to executives and customers.

Cross-Functional Collaboration

• Serve as the primary bridge between design, architecture, DV, emulation, validation, and manufacturing/test teams.
• Ensure pre-silicon verification and post-silicon validation plans are aligned and jointly optimized.
• Collaborate with software and tools teams to provide a world-class bring-up and debug environment.
• Influence design-for-test (DFT) and design-for-validation (DFV) features during pre-silicon phases.

Required Qualifications

• 12+ years of experience in SoC/processor verification, emulation, and/or post-silicon validation, with at least 5 years in technical leadership or management.
• Proven track record owning verification/validation for a complex SoC from early design through production.
• Prior experience in a startup environment—adaptable, flexible, and comfortable leading in fast-paced, rapidly evolving conditions, with the ability to quickly reprioritize as requirements change.
• Deep expertise in:
  • SystemVerilog, UVM, and coverage-driven verification
  • Pre-silicon verification infrastructure and methodologies
  • Emulation/prototyping (Palladium, Veloce, Zebu, FPGA prototyping, etc.)
  • Post-silicon bring-up, validation, test, and debug
• Experience managing internal and external engineering teams (consultants, offshore teams, validation vendors).
• Strong silicon debug skills across digital, analog, timing, and system-level domains.
• Proficiency with scripting (Python preferred) and automation workflows.
• Excellent communication skills with demonstrated ability to influence cross-functional teams and executives.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field (PhD a plus).

Preferred Qualifications

• Experience with processor architectures, memory subsystems, interconnects, and hardware/software co-design.
• Background in DFT, UPF/low-power simulation, or mixed-signal verification.
• Strong network and past working relationships with leading DV and silicon validation partners.